segunda-feira, 10 de abril de 2023

Will it be possible to have a petabit NAND chip?

 To have an economical petabit NAND chip it is compulsory to increase the number of layers to over a hundred thousand but that poses technical challenge as deeper etching of the wells increases errors and also increases the area used for the access ladder to the word lines.

Fig. 1 – Vertical channel GAA and horizontal word-lines

My idea is to create decks with independent power lines and bit lines and without access ladders to word lines.

To do that, first, on each deck, power lines and bit lines are routed to one side of the chip, using inexpensive 40nm node or higher:

Fig. 2 – PL and BL are routed to the side.

Second, independent decks are deposited on top of each other (just as an example, 6 decks in the next figure that is turned side).

Third, memory chips are checked, cut and mounted facing up the side where the access wiring is (to PLs, BLs and WLs).

Finally, wiring between decks is made in a process similar to the fan-in wafer-level packaging using inexpensive 40nm node or higher.

There will be just one power line and a bit line for every two decks (it will be read two decks at a time).

Fig. 3 – Side view to six independent decks, 6x232 = 1392 layers.

In this way, it will be unnecessary to etch the access ladder to the word lines and errors do not propagate from deck to deck due to their independence.

If we flip the chip twice

Power lines will be on one side and bit lines will be on another, perpendicular, side. Then, we no longer need to divert the bit lines that avoids multiple lithographs per deck, decreasing costs.

On the bit line side, we just wire line yes / line no pairs (two decks will be read simultaneously). If, for example, there are 32768 bit lines, they will be read 65536x4 = 262144 bits simultaneously (QLC).

Fig. 4 - Bit lines will be wired in two "lines" (chip side, PL will be in the perpedicular side)

What is the limit number of decks?

There will be no physical limitation to the number of decks. The optimal number of decks will be an economical trade-off between more area versus more layers.

To have a TLC one petabit chip, one will have, a cube 8.5 x 8.5 x 8.5 mm3 (730 decks and 169360 horizontal layers).

HDD are doomed.

Last year I thought that HDDs were going to evolve enough to stand up to SSDs for another ten years but now I don't think so.

After a peak of 651 millions units in 2010, sales dropped to 148 millions units in 2022, a reduction of almost 80%.

Now, I think HDD technology will become irrelevant within 5 years, replaced by NAND technology.

Fig. 5 - HDD sales (see)

20 April 2023

0 comentários:

Enviar um comentário

Twitter Delicious Facebook Digg Stumbleupon Favorites More

Design by Free WordPress Themes | Bloggerized by Lasantha - Premium Blogger Themes | Best Hostgator Coupon Code